Many modern electrical systems include digital circuitry along with analog to digital converters (ADCs or A/Ds) to interface with analog signals such as temperature, pressure, voice, etc., or modulated carriers transmitting information over some medium (analog or digital communication). For many systems, particularly battery-powered user devices, energy efficiency is important. Delta sigma architectures are widely used for high resolution, low speed ADCs as well as for medium resolution, high-speed ADCs. Continuous time delta sigma modulators (CTDSM) are often used for high speed applications requiring a moderate number of bits and are very popular because of their simple design and low power consumption. Continuous time delta sigma modulators include a digital to analog converter (DAC) in feedback circuit to complete a delta sigma loop. A common CTDSM topology is a cascade of integrators and feedback (CIFB) DAC.
Achieving high linearity in high-speed DACs is difficult without very good matching in feedback DACs. Feedback DAC mismatch errors directly contribute to even order harmonic distortion. These errors can be caused by mismatched DAC switches, mismatched clock duty cycles and/or mismatched clock signal rise and fall times. DAC switches, such as MOS transistors are typically biased in saturation to avoid any inadvertent shorting of virtual ground. Switch threshold voltage mismatch or mismatch in switch turn on/off time along with DAC current source parasitic capacitance can lead to imbalance in differential current in forward path integrators of a DSM. Moreover, clock duty cycle mismatch can cause mismatch in current integration. These mismatch errors degrade the DSM operation. For example, mismatch in a CTDSM differential feedback circuit path can lead to high offset errors in the digital output stream of the delta sigma modulator as well as even order harmonic distortion in the DSM output. These DAC error induced offset and even order harmonic distortion problems and poor linearity are not acceptable in many high-speed and high performance systems like automotive radar applications.
Prior solutions include calibrating mismatch errors by creating intentional imbalance in DAC switch drive circuitry in order to cancel out the mismatch effects. In these solutions, offsets are measured and the DAC switch drive levels are trimmed until the mismatch cancels out to a desired level. However, such calibration is done during assembly and testing and requires significant test time to measure non-linearity and then apply a trim code to individual electronic components. Also, the process is iterative may require multiple iterations thereby increasing manufacturing time and cost. Furthermore, mismatch variation across temperature cannot be corrected by these assembly calibration codes, and production calibration does not reduce flicker noise contribution due to DAC switch mismatch.